Hardware-Assisted Verification: Ideal Foundation for RISC-V Adoption
By Jean-Marie Brunet, Siemens EDA
EETimes Europe (November 23, 2023)
HAV is becoming an enabler for the emerging ecosystem based on its ability to run many cycles of software-driven validation.
The semiconductor industry has seen RISC-V go from hype to reality, leading us to where we are today. At a time when RISC-V is being used in many vertical markets, we are seeing production-level implementation and astonishing growth in market adoption. With the instruction set architecture (ISA) and software in an open-source ecosystem, designers have the ability to design a specific, custom instruction set for a single end application, rather than a generic instruction set usable in a wide variety of applications.
RISC-V is here to stay. Now the challenges begin.
The ecosystem for RISC-V or any custom core differs from a well-established ecosystem such as Arm’s. The Arm ecosystem has been used for years by designers who trust the device, the ISA, the software and the verification tools. In contrast, the RISC-V ecosystem usage and experience are immature and don’t yet provide the same level of legacy experience and domain knowledge sharing. Designers using new architectures like RISC-V need to verify corner cases, do excessive software validation and run a higher number of more complex workloads—much more than for established CPU or GPU devices.
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