How to manage dynamic power in a microcontroller using its non-maskable interrupt
How to manage dynamic power in a microcontroller using its non-maskable interrupt To read the full article, click here
By Ajit Basarur, Shantanu Prasad Prabhudesai, and Nazmul Hoda, Ittiam Systems
pldesignline.com (August 06, 2008)
Abstract
As portable systems become increasingly power-conscious, the need for smart power management becomes equally important. Besides the main processor, an auxiliary Microcontroller Unit (MCU) often resides on such systems to take care of house keeping activities such as various user interfaces and a real-time clock (RTC), which has to tick even when the system is powered off.
In this article, we suggest a mechanism to implement power management scheme for the MCU based on system switch on and off states by using its non-maskable interrupt (NMI) pin.
1. Typical embedded system overview.
(Click this image to view a larger, more detailed version)
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- A need for static and dynamic Low Power Verification
- FinFET impact on dynamic power
- Dynamically controlled logic gate design for all power modes
- Making interrupt design firmware friendly
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs