Design Constraint Verification and Validation: A New Paradigm
By Jason Ware, Cadence Design Systems, Inc.
June 18, 2007 -- edadesignline.com
Over the years, Electronic Design Automation (EDA) tools have matured considerably. They now aid in design and verification of all aspects of chip manufacturing. One area that has lagged behind is the validation of design constraints. While chip design, functional verification, timing verification and manufacturing have become highly automated, the writing and verification of design constraints has been largely a tedious, manual process.
Today, we have software that can manage, verify and even create design constraints. This allows designers to reduce design cycle times and improve the quality of the design constraints. Improved constraints mean higher quality silicon, especially at finer geometries like 90nm and below (Figure 1).
1. Today's Constraint Management tools can validate and generate constraints for all stages of the design flow.
An extension of constraint validation is exception generation. A constraint management tool can examine the netlist and find functional false paths. The tool must validate these with a proven formal engine to prove the paths can be declared false. Once the paths are proven as false, they can be removed from the cost-equation and static timing analysis of the synthesis and implementation tools. This frees the optimization engine to concentrate on real paths. The benefit is a smaller, faster, cooler design.
June 18, 2007 -- edadesignline.com
Over the years, Electronic Design Automation (EDA) tools have matured considerably. They now aid in design and verification of all aspects of chip manufacturing. One area that has lagged behind is the validation of design constraints. While chip design, functional verification, timing verification and manufacturing have become highly automated, the writing and verification of design constraints has been largely a tedious, manual process.
Today, we have software that can manage, verify and even create design constraints. This allows designers to reduce design cycle times and improve the quality of the design constraints. Improved constraints mean higher quality silicon, especially at finer geometries like 90nm and below (Figure 1).
1. Today's Constraint Management tools can validate and generate constraints for all stages of the design flow.
An extension of constraint validation is exception generation. A constraint management tool can examine the netlist and find functional false paths. The tool must validate these with a proven formal engine to prove the paths can be declared false. Once the paths are proven as false, they can be removed from the cost-equation and static timing analysis of the synthesis and implementation tools. This frees the optimization engine to concentrate on real paths. The benefit is a smaller, faster, cooler design.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- New Realities Demand a New Approach to System Verification and Validation
- Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
- BCD Technology: A Unified Approach to Analog, Digital, and Power Design
- Design and implementation of a hardened cryptographic coprocessor for a RISC-V 128-bit core
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace