Compiling FPGA netlists for formal verification

Joachim Pistorius and K. Chandrashekar, Altera Corp.
02/06/2006 9:00 AM EST, EE Times
 
Multi-million gate system-on-a–chip (SoC) designs easily fit into today’s FPGAs. Due to the ever increasing demand for more speed, less area, and less power, the transformation of a customer’s RTL description into a bitstream format that can program the FPGA is increasingly complicated. This in turn increases the demand for verifying the design transformations.

Even though FPGAs are reprogrammable, an error detected late in the design cycle, or even after the board has gone into production, can still be very expensive. In addition, some FPGA vendors offer migration to structured ASICs, in which a fabricated design cannot be reprogrammed. Therefore, it is even more important for designs targeted towards structured ASIC device families that implementation errors are caught early in the development phase.

For all of the above reasons, customers want to verify the functional correctness of the RTL-to-bitstream design transformations. Formal methods are becoming increasingly popular in the FPGA design methodology, as they offer several advantages over the traditional method of vector-based simulation. Some of these advantages are shorter runtime, better functional coverage, and no need for test vectors.

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