Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions
The convergence of open RISC-V architectures, real-time hypervisors, and efficient embedded AI frameworks marks a transformative moment in critical space system design.
By Pablo Ghiglino (Klepsydra), Jan Reinhard (Sysgo) and Jean-Didier Noir (Sysgo)
EETimes Europe | August 5, 2025
As modern space missions evolve in complexity, the role of software onboard spacecraft is undergoing a dramatic transformation. Spacecraft are no longer limited to basic telemetry and remote control. Today, onboard computing must support autonomous decision-making, intelligent data reduction, and rapid responses to unforeseen conditions—all while operating under strict constraints on power, size, and reliability. Artificial intelligence and machine learning (AI/ML) are the technologies driving this shift, but implementing them in the harsh, resource-constrained environment of space demands a new breed of embedded computing.
At the center of this evolution lies a fully European initiative combining open-source hardware, certified real-time software, and efficient AI frameworks. It’s a future built on RISC-V processors, safety-critical hypervisors, and edge-optimized AI engines—all integrated into a secure and flexible technology stack designed for space. This article explores how this fully European ecosystem is shaping the future of space autonomy.
Related Semiconductor IP
- RISC-V Debug & Trace IP
- RISC-V IOPMP IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Multi-core capable RISC-V processor with vector extensions
Related Articles
- Creating a custom processor with RISC-V
- Extending RISC-V ISA With a Custom Instruction Set Extension
- A guide to accelerating applications with just-right RISC-V custom instructions
- Let's make RISC-V connected systems synonymous with security
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow