3D-IC Design: The Challenges of 2.5D versus 3D
Samta Bansal, Senior Product Marketing Manager, Cadence Design Systems
EETimes (9/14/2011 11:29 AM EDT)
In October 2010 Xilinx announced its use of a 2.5D through-silicon via (TSV) approach for their Virtex-7 FPGAs. This was followed by announcements from TSMC, Samsung, Nokia, Micron, and Elpida about using 3D-ICs with TSVs, showing that TSV technology has emerged as a proven and viable technology that offers compelling advantages in power, performance, form factor, and time to market. By making it possible to stack analog, digital, logic, and memory dies at different process nodes, 3D-ICs offer what may be the best alternative to the skyrocketing costs of advanced process nodes.
This article examines the terminology associated with 3D-ICs and reviews what 2.5D is, what 3D is, and what the tradeoffs are. It then introduces some 3D-IC design challenges such as system exploration, floorplanning, analysis, and design for test (DFT), and shows how designs will evolve as 3D-IC goes on to become a necessity for managing power, performance, form factor, and cost goals.
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