A modeling approach for power integrity simulation in 3D-IC designs
Vinayakam Subramanian (Apache Design, Inc.) and Jairam Sukumar (Texas Instruments)
4/27/2012 10:10 AM EDT
Designing reliable three-dimensional (3D) system-on-chips (SoCs) is extremely complex, and critical for the next level of integration in silicon design. In 3D integrated circuit (3D-IC) vertical stacked-die architecture, individual die are connected directly by Through-Silicon-Vias (TSVs) and micro-bumps. Simulation of 3D-ICs for power integrity needs to model the 3D structure, including all the ICs and their TSV interconnects. Some challenges include modeling and integrating third-party application SoCs or memories into the current design framework and performing a complete analysis. This article outlines an approach for concurrent analysis of the 3D-IC power grid, as well as a chip model-based analysis, and how analysis based on a chip macro-model can yield the same results as concurrent full-chip analysis, resulting in significant runtime benefits.
To read the full article, click here
Related Semiconductor IP
- Root-of-Trust IP - High-Assurance Security for Advanced and Regulated Applications
- Root-of-Trust IP - Enhanced-Assurance, Configurable Security for Scalable Semiconductor Designs
- Root-of-Trust IP - Compact, Configurable Security for Flexible Semiconductor Designs
- 100-10Gbps Ethernet MAC Controller
- SD Card Controller
Related Articles
- Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
- Memory solution addressing power and security problems in embedded designs
- Reclaiming lost yield through methodical power integrity optimization
- Context Based Clock Gating Technique For Low Power Designs of IoT Applications - A DesignWare IP Case Study
Latest Articles
- LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation
- Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors
- Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library
- A 105 MS/s 4.18 nJ/inference 0.765 mm² Mixed-Signal Streaming ML Engine for Wireless Baseband in 12LP+ FinFET
- Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains