A modeling approach for power integrity simulation in 3D-IC designs
Vinayakam Subramanian (Apache Design, Inc.) and Jairam Sukumar (Texas Instruments)
4/27/2012 10:10 AM EDT
Designing reliable three-dimensional (3D) system-on-chips (SoCs) is extremely complex, and critical for the next level of integration in silicon design. In 3D integrated circuit (3D-IC) vertical stacked-die architecture, individual die are connected directly by Through-Silicon-Vias (TSVs) and micro-bumps. Simulation of 3D-ICs for power integrity needs to model the 3D structure, including all the ICs and their TSV interconnects. Some challenges include modeling and integrating third-party application SoCs or memories into the current design framework and performing a complete analysis. This article outlines an approach for concurrent analysis of the 3D-IC power grid, as well as a chip model-based analysis, and how analysis based on a chip macro-model can yield the same results as concurrent full-chip analysis, resulting in significant runtime benefits.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
- Memory solution addressing power and security problems in embedded designs
- Reclaiming lost yield through methodical power integrity optimization
- Context Based Clock Gating Technique For Low Power Designs of IoT Applications - A DesignWare IP Case Study
Latest Articles
- Hardware-managed heterogeneous high-bandwidth memory and flash in LLM inference systems
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration