3+ ways to design reconfigurable algorithm accelerator in IP block

Related Semiconductor IP

• AXI to UCIe FDI Interface IP
• 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
• 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
• Peripheral Sensor Interface (PSI5) Host Controller
• Link Acceleration Unit

Related Articles

• How to manage changing IP in an evolving SoC design
• Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think
• Four ways to build a CAD flow: In-house design to custom-EDA tool
• Time Interleaving of Analog to Digital Converters: Calibration Techniques, Limitations & what to look in Time Interleaved ADC IP prior to licensing

Latest Articles

• CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
• Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
• Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
• LLM4RTL: Tool-Assisted LLM for RTL Generation
• Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs