10 Favorite FPGA-Based Prototyping Boards
Adam Taylor, E2V
5/10/2016 06:24 PM EDT
Many FPGA development projects end up as custom-designed boards. During the design and development phase, however, using an off-the-shelf development board facilitates hardware-in-the-loop verification and provides for significant risk mitigation of the more challenging technical aspects associated with getting the system up and running.
We can use these boards for a number of different end applications as such no one board is the magic bullet that enables us to use it for all applications. Each time we come to select a board for our project we must consider not only the performance of the FPGA or as you will see SoC mounted on it but also the types and size of memories available, the interfaces available, such as USB, EIA232, GigE, among others, along with user-accessible IO allowing integration with elements of the application.
Let us take a look at 10 interesting boards that can be used across a number of different applications.
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- FPGA-Based Prototyping - "Productivity to Burn"
- FPGA-based prototyping grows up
- How to improve FPGA-based ASIC prototyping with SystemVerilog
- FPGA-based rapid prototyping of ASIC, ASSP, and SoC designs
Latest Articles
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
- Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices