High-Performance Computing gets more energy-efficient data transfer
March 2, 2017 -- The 3D-NoC network-on-chip developed by Leti, STMicroelectronics, and Mentor Graphics under a project coordinated by IRT Nanoelec offers 20% to 40% less energy consumption and higher speeds than other NoCs.
The NoC developed is built on two 28 nm FDSOI stacked circuits, each with 96 processor cores. The cores are integrated on a 65 nm CMOS active interposer layer, which ensures communication between the cores and electrical conversion, reducing the distance between cores to just a few hundred microns. For discrete components on an electronic circuit board, the distance can be several centimeters.
A circuit is currently in fabrication and should be delivered in early 2017. Given the maturity of the technology, it could be transferred to a manufacturer very rapidly.
Related Semiconductor IP
- NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
- NoC Verification IP
- FlexGen Smart Network-on-Chip (NoC) IP
- NoC System IP
- Non-Coherent Network-on-Chip (NOC)
Related News
- LETI Develops 3D Network-on-Chip to Improve High-Performance Computing
- Leti launches new Silicon Impulse FD-SOI Development Program, to Help Designers Broaden the Use of FD-SOI for Low-power Applications
- Leti Joins GLOBALFOUNDRIES' Eco-System Partners With Focus on Supporting 22FDX Platform
- Leti Strains to Improve FDSOI
Latest News
- Chipsolve Technologies Appoints Balaji Kanigicherla as Chairman of the Board
- OXMIQ Raises $35 Million to Scale OxCore™ Architecture
- SOC-E successfully showcases Time-Sensitive Networking (TSN) application for NGWS/FCAS Remote Carrier (Pillar 3)
- Xiphera Strengthens Its Presence in Japan with the Appointment of Yasuhiro Okumura as Country Manager
- TES offers a new DC-DC Split-Pi Boost-Buck Converter IP in X-FAB XT018-0.18µm BCD-on-SOI CMOS