Leti Strains to Improve FDSOI
Peter Clarke
12/17/2015 10:44 AM EST
LONDON—French research institute CEA-Leti has reported on two techniques to put local strain in the silicon channel of a fully-depleted silicon-on-insulator (FDSOI) manufacturing process.
STMicroelectronics and Globalfoundries are championing the FDSOI process as a means to achieve world-class energy efficiency in leading edge integrated circuits without the complexity and expense of FinFET manufacturing.
To read the full article, click here
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related News
- Leti and STMicroelectronics Demonstrate Order-of-Magnitude-Faster FD-SOI Ultra-Wide-Voltage Range DSP
- Leti launches new Silicon Impulse FD-SOI Development Program, to Help Designers Broaden the Use of FD-SOI for Low-power Applications
- LETI Develops 3D Network-on-Chip to Improve High-Performance Computing
- Chameleon cuts staff, plans to improve processor
Latest News
- StarFive and LECARC Forge Partnership to Co-Develop RISC-V Server CPUs and Seize New Opportunities in the Agentic AI Era
- ASICLAND Selected as SK hynix’s Partner for Next-Gen eSSD Development, Establishing a ‘K-Semiconductor Win-Win’ Model
- onsemi to Acquire Synaptics to Enable the Next Generation of Intelligent Systems for Physical AI
- EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution
- Jim Keller: ‘AI Still Obeys the Old Laws of Compute’