JEDEC Advances DDR5 MRDIMM Ecosystem with New Memory Interface Logic and Expanded MRDIMM Roadmap

New DDR5 MRDIMM memory logic standards enable higher bandwidth scaling while JEDEC progresses next‑generation MRDIMM module designs

ARLINGTON, Va.-- April 30, 2026 --JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced milestones from its JC-40 and JC-45 Committees for Logic and DRAM Modules: the publication of a new DDR5 multiplexed rank data buffer (MDB) standard; progress toward a multiplexed rank registering clock driver (MRCD) standard; and continued work on the DDR5 multiplexed rank DIMM (MRDIMM) Gen2 roadmap to enable higher-bandwidth DDR5 MRDIMM designs.

• Published: JESD82-552 (DDR5MDB02) Multiplexed Rank Data Buffer
• Expected soon: JESD82-542 (DDR5MRCD02) Multiplexed Rank Registering Clock Driver
• In progress: MRDIMM Gen2 module standard nearing completion
• In development: Gen2 DDR5 MRDIMM raw card designs targeting 12,800 MT/s and MRDIMM Gen3 module standard development, with the underlying memory interface logic nearing finalization

Published: JEDEC has published JESD82-552: DDR5MDB02 Multiplexed Rank Data Buffer, now available for download from the JEDEC website. The standard defines next-generation data buffer functionality for multiplexed rank DIMM architectures, supporting robust operation as module bandwidth scales.

Expected soon: JESD82-542: DDR5 Multiplexed Rank Registering Clock Driver (DDR5MRCD02) is expected to be published in the near future. This forthcoming standard is intended to further strengthen signal integrity and timing control in DDR5 MRDIMM module designs, complementing JESD82-552.

In progress: The JC-45 Committee is nearing completion of its MRDIMM Gen2 standard, advancing high-performance memory module design to meet increasing bandwidth and system-level efficiency requirements for next-generation computing platforms.

In development: The committee is also developing second-generation DDR5 MRDIMM Gen2 raw card designs targeting 12,800 MT/s, underscoring JEDEC’s commitment to enabling higher data rates and scalable memory solutions for data-intensive applications. JC-45 is also looking ahead to the development of the MRDIMM Gen3 standard.

For more insights, join JEDEC in San Jose this May for its Mobile/Client/Edge and Server/Cloud Computing/AI Forums, featuring in-depth sessions on emerging memory standards and system designs. View agendas and register on the JEDEC website.

“These coordinated efforts in JC-45 reflect JEDEC’s ongoing role in aligning the industry around interoperable, high-performance memory standards that meet the growing demands of AI, cloud computing, and enterprise workloads,” said Mian Quddus, Chairman of the JC-45 Committee and the JEDEC Board of Directors.

JEDEC standards are subject to change during and after the development process, including disapproval by the JEDEC Board of Directors.

About JEDEC

JEDEC is the global leader in the development of standards for the microelectronics industry. Thousands of volunteers representing over 380 member companies work together in more than 100 JEDEC committees and task groups to meet the needs of every segment of the industry, for manufacturers and consumers alike. The publications and standards generated by JEDEC committees are accepted throughout the world. All JEDEC standards are available for download from the JEDEC website. For more information, visit https://www.jedec.org.