Showcasing AI-Driven Analog Design Migration at Samsung SAFE Forum
Earlier this year, I had the opportunity to attend and present at Samsung SAFE Forum (SFF) in San Jose, California, during the “Advanced Technology and Design Infrastructure” session. The session started with a Tech Talk delivered by Sangyun Kim, VP and head of Design Technology, Samsung Electronics, who artfully articulated several important technology insights and trends: advanced FinFET technology and the Samsung technology roadmap, 3D IC and multi-die integration, and design migration solutions to help customers quickly take advantage of the most optimized Synopsys technologies for their applications. Later, the session included partners presentations, which is where I came in.
My presentation titled “Accelerating Analog and Digital Design Migration Using Synopsys.ai” focused on one of Samsung’s key topics: rapid analog design migration challenges. I started my talk by highlighting several key high-value problems our customers and partners are telling us they need help with:
- Rapidly migrating designs to new process technology nodes to keep up with the industry’s relentless and continuous push forward
- Using multi-die integration to extend Moore’s law into the SysMoore era
- Getting to market quickly by ensuring first-time-right silicon
- Delivering highly robust electronic systems, especially for mission-critical applications
To read the full article, click here
Related Semiconductor IP
Related Blogs
- Rambus showcases 56G Multi-Protocol SerDes (MPS) PHY at the Samsung Foundry Forum
- Rambus at the Samsung Foundry Forum
- Applied AI in Analog IC Design Migration
- Analog Design and Layout Migration automation in the AI era
Latest Blogs
- Designing for What Comes Next in AI
- Secure boot on Efinix Titanium Ti60: Getting started with KiviBoot-Tiny
- How Long Does It Take to Port a New AI Model? Minutes Now, and Falling
- PCI Express Security and TEE Integration, Part 1 - Establishing Trust
- World Models at the Edge, in Real Time: V-JEPA 2.1 on the Quadric GPNPU