Video: Cadence Demonstrates PCIe Gen3 Silicon at PCI-SIG Dev-Con (SAS RAID Controller)
July 28, 2011
This video is part one of a two-part series demonstrating the Cadence PCI Express Gen3 IP silicon on the customer's PC board while it's being tested with a LeCroy Protocol Analyzer and Exerciser. In part one, Ashwin Matta, Cadence engineering director, discusses the IP performance and core capabilities of the Cadence PCI Express Gen3 IP captured by the display trace.
To read the full article, click here
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Blogs
- Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features
- According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012
- PCIe Gen4 Test Suite with Spec Linking Demo
- The Future of PCIe Is Optical: Synopsys and OpenLight Present First PCIe 7.0 Data-Rate-Over-Optics Demo
Latest Blogs
- IDS-NoC: A Scalable Interconnect Solution for Modern SoC Design
- Leading-edge AI IC designs demand comprehensive HAV methodologies
- Beyond the Fab: Building Europe’s Next Generation of Semiconductor Champions
- AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP
- Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution