Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features
August 4, 2011
Welcome back for Part 2 of a two-part PCI-SIG video demo featuring Cadence’s PCI Express Gen3 Controller IP advanced capabilities, with a discussion on Single Root I/O Virtualization (SR-IOV). Part 1 was covered in a recent blog post.
What is SR-IOV? Briefly, SR-IOV is a specification that allows a PCIe device to appear to be multiple separate physical PCIe devices. PCI-SIG created and maintains the SR-IOV specification with the goal of having a standard specification to help promote interoperability. One of the milestones achieved for Cadence’s design IP for PCI Express Gen3 is proving SR-IOV interoperability in silicon against an Intel chipset.
To read the full article, click here
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Blogs
- Video: Cadence Demonstrates PCIe Gen3 Silicon at PCI-SIG Dev-Con (SAS RAID Controller)
- Cadence Leads the Way at PCI-SIG DevCon 2025 with Groundbreaking PCIe 7.0 Demos
- Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026
- According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012
Latest Blogs
- IDS-NoC: A Scalable Interconnect Solution for Modern SoC Design
- Leading-edge AI IC designs demand comprehensive HAV methodologies
- Beyond the Fab: Building Europe’s Next Generation of Semiconductor Champions
- AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP
- Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution