According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012
The launch from Cadence of the PCI Express 3.0 Controller IP was officially done about one year ago, and demonstrated at the June 2011 PCI-SIG Developer's Conference, where Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller configuration was shown, implemented in a customer's ASIC.
The associated Verification IP (VIP), made of Compliance Management System (CMS) which provides interactive, graphical analysis of coverage results, and PureSuite which provides the PCIe associated test cases, clearly demonstrate that the acquisition of Denali has greatly helped Cadence to position on the advanced PCIe IP market, with design IP (Controller) and VIP.
To read the full article, click here
Related Semiconductor IP
- PCI Express Gen3 SERDES PHY on TSMC CLN40G
- PCI Express Gen3 SERDES PHY on Samsung 7LPP
- PCI Express Gen3 SERDES PHY on Samsung 28LPP
- PCI Express Gen3 / SATA3 SERDES PHY on Samsung 28FDSOI
- PCIe Gen3 Class SSCG PLL on TSMC CLN16FFC
Related Blogs
- Interface Protocols, USB3, PCI Express, MIPI, SATA... the winners and losers in 2012
- PCI Express Security and TEE Integration, Part 1 - Establishing Trust
- PCI Express takes on Apple/Intel Thunderbolt and 16 Gtransfers/sec at PCI SIG while PCIe Gen 3 starts to power up
- Apple Will Nudge Prices Down in 2012: PC Market Will Collapse
Latest Blogs
- Designing for What Comes Next in AI
- Secure boot on Efinix Titanium Ti60: Getting started with KiviBoot-Tiny
- How Long Does It Take to Port a New AI Model? Minutes Now, and Falling
- PCI Express Security and TEE Integration, Part 1 - Establishing Trust
- World Models at the Edge, in Real Time: V-JEPA 2.1 on the Quadric GPNPU