Pushing to the Limits: Understanding Lane Margining for PCIe
PCI-SIG has built its reputation on delivering high quality PCI Express® (PCIe) specifications that have doubled bandwidth on average every three years, while maintaining full backwards compatibility with prior generations. This is no easy task, and as an organization, we continue to innovate in order to meet the performance requirements of our members and the industry within the power, cost, and high volume manufacturing constraints.
When we set out to design the PCIe 4.0 specification – which doubled bandwidth from 8 GT/s to 16 GT/s per Lane while maintaining backwards compatibility – we realized that system designers would need to know how much signaling margin was actually available in their design in order to squeeze out full 16GT/s performance while taking into account channel loss limits. Of course, while robust high-speed signaling simulations would be required to ensure proper designs, we felt that a test which could be run in the actual physical system would provide confidence on the reliability of the system.
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