PCIe Lane Margining - What changed from Gen4 to Gen6?
With new PCIe 6.0 Base specifications rolled out, the move from NRZ (non-return-to-zero) to PAM4 (4-Level Pulse Amplitude Modulation) is no surprise. To address the Nyquist frequency issues at 64GT/s, which doubles to 32GHz which further causes frequency dependent loss increased to 70dB, PAM4 was introduced.
Use of PAM4 signaling address the issues related to integrity, channel loss and backward compatibility but increased the complexity to verify designs.
Now till PCIe 5.0 for Lane margining at receiver, NRZ (non-return-to-zero) was used. With PCIe 6.0, PAM4 was used instead.
PAM4 is a multi-level signaling technology that transmits two bits per unit interval (UI) as opposed to the conventional NRZ (non-return-to-zero), which transmits only one bit per UI.
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