PCIe Controller IP

The PCI Express® (PCIe®) Controller IP is a highly configurable, performance-optimized core designed for ASIC and FPGA integration. Supporting PCIe Gen1 through Gen6 at data rates up to 64 GT/s, the controller accommodates a wide range of link widths (x1–x16) and protocol features to meet the demands of next-generation SoC, networking, and high-performance computing platforms. The controller seamlessly interoperates with PIPE-compliant PHYs and supports multiple modes including Root Complex, Endpoint, Switch, and Dual-Mode operation.

Engineered for scalability and low latency, the design is verified across emulation, FPGA, and silicon environments, and integrates rich RAS features, power optimization techniques, and AXI-based interfaces for system compatibility.

• Compliant with PCIe 6
• Compliant with PIPE 6.x
• Support FLIT and non-FLIT modes
• Multi-mode operation: Root Complex, Endpoint, Dual-Mode, and Switch
• Flexible core data path: Configurable 256b, 512b, and 1024b core data width
• Support AXI4 and native TLP interface
• RAS features: Timer overrides, error injection, LTSSM debug, ACK/NAK timers
• Low Power Modes: L0p, L1, L1 Substates
• IDE (Integrity and Data Encryption) optional security module
• Support SRIS mode
• Support multiple virtual channels (VCs)

• Broad application fit through support for full PCIe generations and configurations
• Highly scalable architecture to meet bandwidth, power, or area requirements
• Fast time-to-market enabled by thorough verification across multiple platforms
• Configurable datapath and logic reduce gate count for targeted deployments
• Support optional integrity and Data Encryption (IDE)

• Data Center and Edge AI Accelerators;
• High-performance Computing (HPC);
• Network Interface Cards (NICs);
• Enterprise-grade FPGA Solutions;
• NVMe

• Verilog RTL source code
• Full documentation
• Lint, synthesis, and STA scripts
• Simulation environment
• FPGA reference design