Navigating the Complexity of Address Translation Verification in PCI Express 6.0
Geeta Arora, Cadence
Controller + ATC + ATS + DTI · RC/EP · x1–x16 · 1 GHz · PCI-SIG certified
PCIe Gen 6 Controller operating at 32 GT/s in non-flit mode. ATC, ATS, and DTI pre-integrated: no separate address translation IP required. PCI-SIG certified at 32 GT/s.
Technical details
| Host interface | SFI · AXI4 · CPI · CHI |
| Power management | L0s · L1 · L1ss · L2 |
| DTI boundary | Shared with CXL 3.0 |
| Process nodes | TSMC · Samsung · Intel |
| Sign-off | Siemens Questa |
| Silicon | IO silicon |
Key specifications
| Protocol | PCIe 6.0 (32 GT/s (non-flit mode)) |
| Modes | RC and EP, single instance |
| Link widths | x1 x2 x4 x8 x16 |
| Frequency | 1 GHz target |
| ATC/ATS | Pre-integrated |
| Certification | PCI-SIG PCIe 5.0 |
PCIe Gen 6 Subsystem is a PCI Express IP core from Signature IP Corporation listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.