Learn more about Single-Protocol PHY IP core
In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.
Enter the Inner Sanctum of RapidIO: Part 1
Networking software key to PICMG 2.16 optimization
One of the major barriers for Semiconductor IP commercialization is to provide evidence for an IP’s quality. A common approach by IP vendors is to prove the quality of their IP in a test chip. Usually the Die contains the IP block separated from the System-on-a-Chip (SoC) . It is, though, uncertain how the block will function in ASSP and ASIC products, potentially damaging its perceived commercial value.
Understanding the MAC impact of 802.11e: Part 1
High-Speed Serial fully digital interface between WLAN RF and BB chips
