PCIe Gen 6 IP Core

64 GT/s PAM4 interface with FLIT mode encoding — the industry's most advanced PCIe generation for AI training clusters, CXL memory expansion, and next-gen data center platforms.

PCIe Gen 6 doubles the throughput of Gen 5 by adopting PAM4 modulation and FLIT-mode encoding — delivering 64 GT/s per lane and 256 GB/s peak bidirectional bandwidth in a ×16 configuration.

Xtremesilica's Gen 6 IP core implements the complete PCIe 6.0 Base Specification including the new FLIT-based transaction layer, L0p low-power link state, and 1b/1b FEC. The core is delivered as synthesizable SystemVerilog RTL compatible with all major FPGA families and any ASIC process node from 180 nm down to 3 nm.

Full backward compatibility ensures seamless operation with existing Gen 1 through Gen 5 devices, protecting your platform investments while enabling next-generation performance.

64 GT/s PAM4 Signaling

PAM4 modulation doubles bandwidth per lane versus NRZ, delivering 64 GT/s while maintaining full backward compatibility with Gen 1–5 devices.

FLIT Mode Encoding

Fixed 256-byte FLIT-based transaction layer with optional 1b/1b FEC. Eliminates variable-latency TLP framing, enabling ultra-low, deterministic latency.

Scalable x1–x16 Lane Width

Compile-time lane-width parameter supports x1, x2, x4, x8, x16 configurations with matching AXI4-Stream interface widths of 64–2048 bits.

L0p Low-Power State

New PCIe 6.0 L0p partial lane-width power state reduces dynamic power by up to 50% when full bandwidth is not required, ideal for power-sensitive deployments.

CXL 3.0 Ready

PCIe Gen 6 is the physical layer for CXL 3.0. Our IP includes CXL mode negotiation support for memory-coherent accelerator and memory-expansion use cases.

Advanced Error Reporting

Full PCIe AER support, MSI/MSI-X interrupts, hardware-assisted error recovery, and real-time performance counters with optional ILA/SignalTap hooks.

AI Training Clusters

• Connect GPUs and NPUs at 256 GB/s for large-model training with minimal host-accelerator bottleneck.

CXL Memory Pooling

• PCIe 6.0 underpins CXL 3.0 for cache-coherent, disaggregated memory across multi-host systems.

NVMe Gen 6 SSDs

• Storage controllers leveraging full Gen 6 bandwidth for all-flash arrays and latency-critical applications.

SmartNIC / DPU

• Data-plane offload NICs requiring maximum PCIe throughput for 400G and 800G Ethernet line rate.

HPC Interconnect

• Scientific computing clusters connecting FPGAs, custom accelerators, and CPUs at maximum bandwidth.

Automotive ADAS

• High-bandwidth sensor-fusion SoCs for advanced driver-assistance and autonomous driving platforms.

Hyperscale Cloud

• Custom cloud ASICs replacing merchant silicon with in-house SoCs optimized for Gen 6 performance.

5G/6G Baseband

• Fronthaul and backhaul processing units requiring ultra-high-bandwidth PCIe bus connectivity.

FPGA Implementation

• Xilinx Vivado project + IP Integrator BD
• Altera Quartus + Platform Designer component
• Microchip Libero SoC SmartDesign
• Platform-specific XDC/SDC/PDC constraints

Custom ASIC Implementation

• Synthesizable RTL (SystemVerilog)
• SDC timing constraints
• Synopsys / Cadence synthesis scripts
• ARM / RISC-V SoC integration reference

Verification Suite

• UVM testbench with 100% functional coverage
• PCIe 6.0 compliance test suite
• Directed + constrained-random regression
• Interoperability test report

Documentation

• Architecture & micro-architecture spec
• Register map & programming guide
• FPGA integration quick-start guide
• Linux / RTOS driver source & guide