Hardware-Assisted Verification: The Real Story Behind Capacity

By Vijay Chobisa, Senior Director of Product Management, Hardware Assisted Verification, Siemens EDA

February 3, 2025

While design engineers contemplate the power, performance and area calculation of an SoC design, their verification counterparts are thinking about whether the hardware emulation and prototyping platform available to them has enough capacity to complete the system-level verification task.

This is particularly true for verifying hardware functionality with complex software workloads. Here is where the concept of usable capacity is an important metric and often misunderstood—especially in the era of skyrocketing gate counts (2.5D- and 3D-IC stacking and chiplets) and massive software workloads. Verification engineers need to know, up front, that their hardware verification platform delivers required usable capacity to verify the SoC at the system level.

To verify large, complex designs like these, verification teams need a platform that can handle capacity scaling in a deterministic and repetitive way. For example, emulating 10 one-billion gate designs versus one 10-billion gates is different and poses significant scaling challenges for both the hardware and software.

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