CXL 3.1: How Evolving CXL Standards are Pushing Interconnects to Even Higher Performance

By Synopsys, Inc.

July 3, 2024

First introduced back in 2019, the Compute Express Link (CXL) is an open industry-standard interconnect between processors and devices such as AI accelerators, memory buffers, smart network interfaces, persistent memory, and solid-state drives. As an industry-standard interface, CXL promotes interoperability between different hardware components from various manufacturers, reducing compatibility issues and allowing for a more diverse and competitive market for data center hardware.

Although it was launched only 5 years ago, much has changed in our world since then, not the least of which is the expanding workloads of data center and high-performance computing environments that power the ever-expanding machine learning and artificial intelligence solutions being used to enhance our lives.

At its core, CXL offers coherency and memory semantics with bandwidth that scales with PCIe while achieving significantly lower latency than PCIe. Read on to learn how leveraging compliant CXL IP allows designers to stay at the forefront of technological advancements and meet market demands and evolving industry standard. This blog will cover how the latest updates in the CXL 3.1 standard include new security features, as well as how it continues to provide the capabilities for memory pooling for next-generation infrastructures.

To read the full article, click here