Vendor: Analog Bits Inc. Category: PLL

PCIe Gen3 Class SSCG PLL on TSMC CLN16FFC

The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…

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TSMC 16nm FFC View all specifications

Overview

The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 serial bus standard where SRIS (Separate RefClk Independent Spread-spectrum clock generation) is required. This SSCG PLL is designed for digital logic processes and use robust design techniques to work in noisy SoC environments.

The SSCG PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and 1.8V IO devices. Eliminating band-gaps and integrating all on-chip components such as capacitors helps the jitter performance significantly and reduces stand-by power.

The SSCG PLL macro includes VDD and VDDA power detectors, which automatically shut down the macro when either rail is not up.

SSCG PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 25 100 MHz Output Frequency FOUT 100 500 MHz Output Duty Cycle tDO 45 55 % Lock Time tLOCK 100 µs Reset Time tRESET 1 µs PLLOUT Output Random Jitter RJO 1 ps-RMS Area (drawn) A 0.062 sq. mm Total Power (unloaded) IDD 16 mW Operational Voltage (Digital) VDIG 0.72 0.8 0.88 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V Operational Temperature TOP -40 25 125 C Table 1: SSCG PLL Operational Range SSCG PLL Functional Specification The phase-locked loop (PLL) block is provided as a drop-in functional block. The PLL accepts input frequencies of 25MHz or 100MHz, and generates output frequencies of 100MHz, 125MHz, 250MHz, or 500MHz.

Key features

  • High performance design emphasis for meeting low jitter requirements in PCI Express applications
  • Implemented with Analog Bits’ proprietary architecture
  • Low power consumption
  • Spread Spectrum Clock Generation (SSCG) and tracking capability
  • Requires no additional on-chip components or band-gaps, minimizing power consumption
  • Excellent jitter performance with optimized noise rejection

Silicon Options

Foundry Node Process Maturity
TSMC 16nm FFC —

Specifications

Identity

Part Number
PCIe Gen3 Class SSCG PLL on TSMC CLN16FFC
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Product Sheet Download

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Provider

Contact Analog Bits Inc.

Learn more about PLL IP core

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Frequently asked questions about PLL IP cores

What is PCIe Gen3 Class SSCG PLL on TSMC CLN16FFC?

PCIe Gen3 Class SSCG PLL on TSMC CLN16FFC is a PLL IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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