Cache Coherent Verification - New Features in AMBA CHI
May 31, 2021
Coherent Hub Interface, popularly known as CHI, is an Interface specification that is part of 5th generation of AMBA® protocols (AMBA® 5) from Arm, released in 2013. AMBA® 5 CHI defines the interfaces for connection of fully coherent processors and dynamic memory controllers, to high performance non-blocking interconnects.
AMBA®CHI-E built on top of existing AMBA® CHI-D (Issue D) specification (refer to our blog on AMBA®CHI-D), introduces the support for– a set of new transactions, exclusive access features, transaction optimizations, series of performance throughput improvement features and key Arm architecture features.
Some of the new features include:
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Related Semiconductor IP
- Verification IP for Arm AMBA CHI Protocol
- Simulation VIP for AMBA CHI
- CXL 3.0 Controller
- Ncore Cache Coherent Interconnect IP
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Related Blogs
- Synopsys AMBA CHI C2C System Verification Solutions
- A Comparison on Different AMBA 5 CHI Verification IPs
- Verification Sanity in Chiplets & Edge AI: Avoid the “Second Design” Trap
- Ecosystem Collaboration Drives New AMBA Specification for Chiplets
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