Breaking Down the "Make vs. Buy" Barriers for IP
As the fabless era disaggregated EDA and IP offerings, there are areas where in- house development is still the norm, even with today’s $2.5B IP industry. One of these is on-chip network – connecting the IP cores and memory subsystem.
On-chip interconnect or networks-on-chip (NoCs), in many companies, is still regarded as a part of the IP that can be internally developed for SoCs. With deeper process nodes, such as 28nm, enabling device convergence, more cores are included in the SoC, accelerated further by subsystems.
Related Semiconductor IP
- NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
- NoC Verification IP
- FlexGen Smart Network-on-Chip (NoC) IP
- NoC System IP
- Non-Coherent Network-on-Chip (NOC)
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- UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics
- The Next-Generation UCIe IP Subsystem for Advanced Package Designs
- Silicon IP for the Final Frontier
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