Automatic Generation of a Network-on-Chip Interconnect
This post discusses the network-on-chip (NoC) approach and explains how Agnisys can help you generate NoCs automatically for your designs.
Vendor:
Truechip Solutions
Category:
Network-On-Chip
NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
Truechip's NoC Silicon IP provides chip designers and architects with an efficient way to connect multiple TileLink based master …
Overview
Truechip's NoC Silicon IP provides chip designers and architects with an efficient way to connect multiple TileLink based master and slave devices with reduced latency, power, and area. NoC Silicon IP also helps to reduce the usage of interconnecting wires and resources inside the chip.
Key features
- Complex network with acyclic agent graph (DAG). Layered and parallel NOC is also supported.Any number of master and slave port is supported. Each port can be configured individually.AMBA AHB3-Lite,5; AMBA AXI 3, 4, 4-Lite,4-Stream, 5,5-Lite,5-Stream, AMBA APB 2,3,4,5 TileLink Tl-UL, Tl-UHConfigurable memory map for different access types of memory regions.Support for different protocol for master and slave port interface.Each port data width can be different. Apart from data, other protocol supported signal can also different width.Early response possibleSupport different phase shifteded frequencies for each Master and SlavesPort priority, Programmable register, Keeper countSupport physical address conversion through NOCWithin minimum latency req or rsp can propagate through NoCBoth little & high endianness is supportedInterleaving support, Out of order transfer , Exclusives supports in AXI portSecure TransferBeat TransferNon contiguous addressEnable bufferingArithmetic and logical transferBack to back transfer supports in AHB
Block Diagram
NoC Silicon IP block diagram
Benefits
- Available in native Verilog (RTL).
- Unique development RTL coding technique to ensure the highest levels of quality for lower latency, highest throughput and lesser area.
- Synthesis & CDC are clean up.
- Verified with expert team using comprehensive and Regression Test Suites.
- Consistency of interface, installation, operation, and documentation across all our IPs
- 24X5 customer support
- Unique and customizable licensing models
What’s Included?
- NoC Matrix (Crossbar/Mesh) & NoC Port (AXI/AHB/APB/Tilelink)
- IP generator & config tool
- Verilog Test Environment with Verilog Testcases
- IP analysis reports
- Linting report
- Synthesis report
- IP-XACT RDL generated address map
- Simulation script
- IP Block Guide
- Quick Start Guide
Specifications
Identity
Part Number
NoC Silicon IP
Vendor
Truechip Solutions
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about Network-On-Chip IP core
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Network-on-Chip (NoC) architectures have become the standard interconnect fabric for many-core systems, yet most proposals face a fundamental trade-off between latency, area, and congestion management. This paper presents HyNoC (Hybrid Network-on-Chip), an open-source NoC architecture that combines circuit-switch path establishment with wormhole data transfer, targeting distributed computing systems built around VLIW processor cores on FPGA.
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Why verification matters in network-on-chip (NoC) design
In this article, we will dive deeper into a comprehensive methodology for formally verifying an NoC, showcasing the approaches and techniques that ensure our NoC designs are robust, efficient, and ready to meet the challenges of modern computing environments.
SoC design: When a network-on-chip meets cache coherency
Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.
Frequently asked questions about NoC IP cores
What is NoC Silicon IP for RISC-V based chips supporting the TileLink protocol?
NoC Silicon IP for RISC-V based chips supporting the TileLink protocol is a Network-On-Chip IP core from Truechip Solutions listed on Semi IP Hub.
How should engineers evaluate this Network-On-Chip?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Network-On-Chip IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.