USB3.1 transceiver IP with PMA and PCS layer
With sophisticated architecture and technology, the USB3.1 transceiver IP with PMA and PCS layer is designed for low power and hi…
- Single-Protocol PHY
USB3.1 transceiver IP with PMA and PCS layer
With sophisticated architecture and technology, the USB3.1 transceiver IP with PMA and PCS layer is designed for low power and hi…
IP
28nm HPC+ USB3.1 gen2 PHY(10Gbps)
28nm HPC+ USB3.1 gen2 PHY(10Gbps)
28nm HPC USB3.1 gen2 PHY(10Gbps)
28nm HPC USB3.1 gen2 PHY(10Gbps)
Configurable PCI Express 4.0 Link Controller
The Renesas PCIe 4.0 Dual Mode Link Controller IP is compliant with the "PCI Express (PCIe) 4.0 Base Specification".
USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in TSMC 28HPC+
This PHY IP supports both USB 3.1 Gen1 & Gen2.
USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC
It supports both USB 3.1 Gen1 and Gen2 with this PHY IP.
USB 3.1 Gen1 / Gen2 Device Controller IP
USB 3.1 Device controller is a configurable core and implements the USB 3.1 Device functionality that can be interfaced with thir…
As the demand for higher data rates and increased serial I/O density intensifies, the performance requirements for next-generatio…
The USB3.2 Verification IP provides an effective & efficient way to verify the components connected with USB3.2 interface of an I…
USB3.x Hub interface provides full support for the USB3.x synchronous serial interface, compatible with USB 3.0/3.1/3.2 specifica…
USB3.x Host interface provides full support for the USB3.x synchronous serial interface, compatible with USB 3.0/3.1/3.2 specific…
USB3.x Device interface provides full support for the USB3.x synchronous serial interface, compatible with USB 3.0/3.1/3.2 specif…
The xHCI Verification IP targets the following three vendors: 1.
USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in SMIC 14SF+
With this PHY IP, it supports both USB 3.1 Gen1 and Gen2.
Accelerated confidence in simulation-based verification of RTL designs with USB interfaces: UCM2, USB3.1, USB3.2, USB-C, Other US…
Proven PHY IP for USB3.1 with supporting multi-protocol feature The ® IP for 10Gbps Multi-Protocol PHY simplifies the design proc…
USB 3.1 Type-C PHY IP, Silicon Proven in TSMC 55ULP
USB3.1Type-C PHY IP is a high performance high speed SERDES IP designed for chips that perform high bandwidth data communication …
USB 3.1 Gen1 / Gen2 Host Controller IP
USB 3.1 Host Controller is compliance with USB3.1 specification, Revision 1.0 and all associated ECN’s, USB specifications Rev 2.…
USB 3.1 is the most recent version of the USB (Universal Serial Bus) standard for connecting electronic devices in host and devic…