16-bit, 160MSPS ADC - GF 22 nm
The A16B160M is an ultra low-power, high-performance analog to digital converter (ADC) intellectual property (IP) design block.
Lossless & Near-Lossless JPEG-LS Decoder
The JPEG-LS-D core implements a efficient and low-power, lossless and near-lossless image decompression engine that is compliant …
PMCC_XCM_64x64_D IP block is a low-power array of 1GHz clocked Cross-Correlator cells that are synchronously acquiring two sets o…
8/10/12-bit Extended JPEG Encoder with Optional Video Rate Control
The JPEG-E-X core is a standalone and high-performance 8-bit Baseline and 10/12-bit Extended JPEG encoder for still image and vid…
AES 128/256 Encryption - Symmetric Security Range
The family of IPX-AES IP-Cores provides an efficient FPGA implementation of the Encryption Standard (AES).
The L6GDA10B054M is a 10-bit, current-output digital-to-analog converter(DAC), which was designed with a 65nm 1P6M CMOS technolog…
Serial Front Panel Data Port (sFPDP) IP Core
The sFPDP core provides a IP solution for the VITA 17.1-2015 sFPDP specification.
High Dynamic Range (HDR) Pipeline
The logiHDR is an Ultra High Definition (UHD) HDR pipeline designed for digital processing and image quality enhancements of the …
UHD Image Signal Processing (ISP) Pipeline
The logiISP-UHD Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD) ISP pipeline designed for digital proc…
Image codec/encoder/decoder (Customizable) - ISO/IEC 10918-1 JPEG standard
Supported Standards ISO/IEC 10918-1 JPEG standard Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pi…
1394b FPGA Link Layer Controller
The FireCore Basic is targeted for applications with up to S3200 data transmission requirements and for designs with a non-PCI Li…
The JPEG-XL-E implements an image compression engine compliant to the JPEG XL, ISO/IEC 18181 standard.
Motion-adaptive Video Deinterlacer IP Core
The DEINTERLACER_MA IP Core is a studio quality 24-bit RGB video deinterlacer capable of generating progressive output video at a…
The JPEG2K-E core is a still image and video encoder that implements Part 1 of the JPEG 2000 standard.
sFPDP IP Core is based on ANSI/VITA 17.1-2003 Standards.
12-bit 1-channel 44/70/90 MSPS pipeline ADC
180TSMC_ADC_13 is a low-power high-speed 12 bit ADC that employs high-performance differential pipeline architecture.
12-bit 1-channel 20 to 100 MSPS ADC
The low-power high-speed 12-bit ADC employs a high-performance differential pipeline architecture.
12-bit 4-channel 20 to 100 MSPS ADC
Quad-channel 12-bit 20 – 100 MSPS ADC contains four ADC channels, LVDS receiver, reference voltages and reference currents circui…
14-bit 1-channel 100/125 MSPS pipeline ADC
The high-speed 14-bit ADC employs a high-performance differential pipeline architecture.
14-bit 1-channel 50 MSPS pipeline ADC
The ADC has built on pipelined architecture.