Motion-adaptive Video Deinterlacer IP Core

The DEINTERLACER_MA IP Core is a studio quality 24-bit RGB video deinterlacer capable of generating progressive output video at any resolution up to 2¹⁶ x 2¹⁶ pixels. The design is fully programmable and supports any desired interlaced video format.

The design allows for three possible deinterlacing schemes. These are: weave, bilinear interpolation or motion-adaptive interpolation. The weave approach applies no filtering and may be useful to obtain a 'raw' interlaced format for subsequent processing. The other two methods are classed as 'inter-field' interpolation methods as spatial filtering is performed between both odd and even fields to achieve a clean and progressive output. The relative merits and disadvantages of each scheme are discussed further into the document.

The deinterlacer core features a fully integrated video frame buffer. This buffer is completely 'elastic' and will dynamically skip and/or repeat frames depending on the input and output frame rates. All frame buffer management is handled internally with the provision of a simple memory interface for storing odd and even fields off-chip. The memory interface is 128-bits wide and is completely generic. All memory transfers are sequential bursts of N x 128-bit words and may be adapted for connection to a variety of memory types such as SDRAM, DDR2 or DDR3.

The input video interface is synchronous to the system clock. Input pixels are sampled on the rising clock-edge of clk with the signals pixin_field and pixin_vsync identifying the field number and the first pixel of each field. All signals are qualified by pixin_val asserted high. The input video interface is non-stallable.

Output pixels are also synchronous with the system clock and are generated in accordance with a simple valid-ready streaming protocol. The output pixels and sync flags are transferred at the deinterlacer outputs on a rising clock-edge when pixout_val and pixout_rdy are both active high. If required, the application circuit may assert pixout_rdy low to stall the flow of output pixels.

• Synthesizable, technology independent soft IP Core for FPGA, ASIC and SoC devices
• Supplied as human readable VHDL (or Verilog) source code
• 24-bit RGB video inputs synchronized to the system clock  (Option to support YCbCr video formats if required)
• 24-bit RGB video outputs synchronized to the system clock
• Generates clean and progressive output video without combing  or tearing
• Excellent vertical resolution and much better than intra-line  interpolation methods
• Supports three different deinterlacing modes including: Classic  weave, inter-line interpolation and interpolation adapted for motion between fields
• Supports all interlaced video formats such as: 480i, 576i, 1080i  etc.  All modes are real-time programmable
• Integrated frame buffer dynamically skips and repeats frames in order to adapt to the desired input and output frame rates
• Diagnostic flags asserted in the event of an input or output buffer overflow
• Simple generic memory interface suitable for SDRAM, DDR, DDR2, DDR3 etc.
• Fully pipelined architecture with simple flow-control. Compatible with all other Zipcores video IP, AXI4-stream and Avalon-ST
• Supports 200MHz+ operation on basic FPGA platforms

• Studio-quality video de-interlacing
• Conversion of 'legacy' SDTV formats to HDTV video formats
• Generating progressive RGB video via inexpensive PAL/NTSC decoder chips
• Digital TV set-top boxes.  Industrial imaging.  Automotive, home and personal media solutions