Vendor: LeoLSI Category: DAC

65nm 10bit 250MSPS DAC

The L6GDA10B054M is a 10-bit, current-output digital-to-analog converter(DAC), which was designed with a 65nm 1P6M CMOS technolog…

10 Bit GlobalFoundries 65nm 6LPe View all specifications

Overview

The L6GDA10B054M is a 10-bit, current-output digital-to-analog converter(DAC), which was designed with a 65nm 1P6M CMOS technology.

The L6GDA10B054M has current steering architecture with differential outputs. It uses 4 linear bits and 6 binary bits, all of which are generated from within the current source array. This results in reduced glitch energy and non-linearity error at the output.

The L6GDA10B054M operates with analog power supply ranging from 3.0V to 3.6V, and its output range covers from 0V to 1.4V. The DAC features the sampling rate of 250MHz over industrial temperature range (-40 ℃ to +85℃) and occupies the core cell area of 0.083mm^2.

Key features

  • 65nm 1P6M CMOS technology
  • 10-bit resolution
  • Maximum 250MHz conversion rate
  • 3.3V analog power supply
  • 1.2V digital power supply
  • Output load : 75Ohm
  • Current consumption : 28mA
  • DNL / INL : ±0.5 /±1.0 LSB
  • Power-down current : < 1uA
  • Core cell area : 0.083mm2

Block Diagram

Benefits

  • Low power
  • Low area
  • Wide output range
  • High performance

Applications

  • Arbitrary waveform generators (AWGs)
  • Direct digital synthesis
  • Imaging applications
  • LCD contrast and backlight brightness control
  • Power supply voltage adjustment

What’s Included?

  • Datasheet, Verilog DB, GDS, CDL, Phantom Cell, Test Spec, sample

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 65nm 6LPe

Specifications

Identity

Part Number
L6GDA10B054M
Vendor
LeoLSI
Type
Silicon IP

Analog

Resolution bits
10 Bit

Provider

HQ: Korea

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is 65nm 10bit 250MSPS DAC?

65nm 10bit 250MSPS DAC is a DAC IP core from LeoLSI listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP