14-bit 1-channel 50 MSPS pipeline ADC

The ADC has built on pipelined architecture. Pipelined ADCs consist of series-connected stages, each stage of the pipeline except the last, consists of parallel low-resolution ADC. This ADC is connected to the switched-capacitors DAC and an interstage residue amplifier (multiplying DAC). The amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. The output block aligns intermediate data in each stage, forms output code, and passes completed data to the output buffers.
The ADC consists of a reference currents and voltages circuit, LVDS clock receiver, ADC core and output logic. The ADC requires 1.62 ÷ 1.98 V analog supply and 0.9 ÷ 1.1 V, 1.62 ÷ 1.98 V digital supplies. The ADC supports standby mode which provides state with minimum power consumption.
The device is manufactured on TSMC 90 nm MS CMOS technology.

• TSMC 90 nm MS CMOS
• 14-bit pipelined ADC
• Single channel
• Conversion rate 50 MSPS
• Different power supplies for digital (1 V and 1.8 V) and analog (1.8 V) parts
• Low standby current <5 uA
• Low power dissipation 171 mW
• Spurious-free dynamic range 77 dB
• Portable to other technologies (upon request)

• Optical networking
• Test equipment
• Portable ultrasound and digital beam-forming systems
• Telecommunication systems
• High quality imaging video systems

• Schematic or NetList
• Abstract model (.lef and .lib files)
• Layout view (optional)
• Behavioral model (Verilog)
• Extracted view (optional)
• GDSII
• DRC, LVS, antenna report
• Test bench with saved configurations (optional)
• Documentation