5G IP Listing

Multi-Protocol AMBA Support - Advanced Routing & Arbitration - Virtual Channel Deadlock Avoidance - Unlimited Scaling

• Network-On-Chip

MAC/PCS/FEC Solutions up to 1.6T

• Controller
• Ethernet 1.6T

The PLL5G150F is an ultra-low power phase locked loop (PLL) intellectual property (IP) block.

• GlobalFoundries
• 22nm
• Silicon Proven

PentaG-NTN is a 5G Non Terrestrial Network (NTN) modem IP subsystem optimized for satellite user terminals operating in LEO and M…

• Cellular

The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.

• Multi-Protocol PHY

MACsec solution for data center, service providers, 5G and AI The MACsec-IP-364 is a MACsec/IPsec engine developed specifically f…

• MACsec

Dubhe-90 is a high-performance commercial RISC-V CPU Core IP that is deliverable.

• RISC-V

The PLL5G250F is an ultra-low power phase locked loop (PLL) intellectual property (IP) block.

• GlobalFoundries
• 22nm
• Silicon Proven

ASIC proven high-performance, feature-rich network interface solution designed to deliver reliable, low-latency Ethernet connecti…

• Ethernet

The USXGMII PCS IP provides the logic required to integrate a USXGMII-M IP into any system on chip (SoC).

• Single-Protocol PHY

A combined silicon agnostic implementation of the PCS layer compliant with Ethernet standard IEEE 802.3-2018 and CPRI Specificati…

• Multi-Protocol PHY
• Mature
• Available
• IEEE 802.3

scalable and silicon agnostic implementation of the interoperable O-RAN WG4 defined 7.2x interface ORAN IP core is a scalable and…

• Cellular

The Symmetric Cryptographic Intel® FPGA IP is a hard IP core implementing AES and SM4 encryption and decryption.

• Symmetric Crypto

Coordinate the actions of disparate electronic systems that must be synchronized in time with Intel® PTP Servo, which employs har…

• IEEE-1588 / PTP

The MACsec Intel® FPGA IP core implements the IEEE Media Access Control Security standard as defined in 802.1AE (2018) as fully c…

• MACsec

The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device re…

• Single-Protocol PHY

Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels.

• Channel Coding

The UCIe Chiplet IP offers a cutting-edge solution for seamless, low-latency data transfer between dies and chips, enabling heter…

• UCIe

Size optimized, silicon agnostic IP core suitable for line rates upto 25G eCPRI core is a scalable and silicon agnostic implement…

• CPRI

mature, silicon proven and silicon agnostic IP core conforming to CPRI 7.0 specifications The Common Public Radio Interface (CPRI…

• CPRI