ORAN IP core

Highly scalable and silicon agnostic implementation of the interoperable O-RAN WG4 defined 7.2x interface

ORAN IP core is a highly scalable and silicon agnostic implementation of the interoperable O-RAN WG4 defined 7.2x interface for deployment in O-DU and O-RU products, targeting any ASIC, FPGA or ASSP technologies.

The ORAN over eCPRI implementation builds on long-time experience designing CPRI and Radio-Over-Ethernet solutions for fronthaul and delivers a flexible engine that is prepared for tight integration with software applications.

The IP is designed to meet or exceed the requirements of radio systems, base band systems, fronthaul switches or advanced test systems. The speed optimized core can handle any solutions reaching from the “small footprint” to the most complex applications running 25 Gbps. The IP can dynamically be configured to handle wireless multi-mode radio systems enabling high-performance throughputs required by 4G and 5G wireless solutions.

Richly Featured

• Support for frequency-domain IQ transport
• Supports 10G/25G Ethernet MAC ports
• O-RU and O-DU variants available
• Multiple Section Extension Types Supported
• Wide flexibility for configuring

Silicon Agnostic

• Targeting both ASICs and FPGAs

• Test Environment: ORAN IF IP is Tested in UVM regression for full functional coverage
• Silicon Agnostic: Designed in Verilog and targeting ASICs and FPGAs
• System Integration: Integration support with Ethernet components for quick and efficient  deployment
• Active Support: All support is actively provided by engineers directly

• The IP Core can be delivered in Source code or Encrypted format.
• The following deliverables will be provided with the IP Core license:
  • Solid documentation, including User Manual and Release Note.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Timing Constraints in Synopsys SDC format.
  • Access to support system and direct support from Chip Interfaces Engineers.
  • Synopsys Lint and CDC (optional)