LatticeMico32 Open, Free 32-Bit Soft Processor
The LatticeMico32™ is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensin…
- CPU
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
LatticeMico32 Open, Free 32-Bit Soft Processor
The LatticeMico32™ is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensin…
Crystal oscillator - UMC 0.18um
Crystal oscillator 32.768KHz
The Rambus Multi-Port Front-End Core from Rambus provides a multi-port interface to Rambus Memory Controller Cores.
Asynchronous Communications Interface Adapter (ACIA)
The following information applies to both the Chip and Core versions of this 65xx brand microprocessor family member.
Peripheral Interface Adapter (PIA)
The following information applies to both the Chip and Core versions of this 65xx brand microprocessor family member.
Soft errors occur when high-energy charged particles alter the stored charge in a memory cell in an electronic circuit.
The HiGig™ MAC transmits and receives data between a host processor and a HiGig™ / Ethernet network that enables networking custo…
Tri-Speed Ethernet MAC Core IP
The Tri-Speed Ethernet Media Access Controller (TSMAC) IP core can be configured to operate in either the Gigabit mode (1000Mbits…
16 bits sigma-delta ADC - UMC 0.18um
16 bits 40kS/s sigma-delta ADC.
Power-on reset for 1.8V. - UMC 0.18um
Power-on reset circuit monitoring 1.8V supply.
Low-noise bandgap reference - TowerJazz 0.18um
Low-noise bandgap reference
The multiplier operation is essential and abundant in DSP Applications.
D/AVE 2D is a 2D GPU Hardware IP Core, optimized for easy integration into FPGAs and ASICs.
Open source version of the UltraSPARC T1 processor
OpenSPARC T1 is the open source version of the UltraSPARC T1 processor.
Aliathon’s VT/TU Mapper performs the insertion and extraction of PDH signals into or from multiple VT/TU paths.
syn1588® enabled IEEE 1588 compliant clock synchronisation
The syn1588® Clock_M IP core offers the full syn1588® technology with a suitable number of trigger and IO events supported.
ADPCM (Adaptive Differential Pulse Code Modulation) is used for speech compression of 64 kbit/s PCM data.
Polybus offers a family of InfiniBand Link Layer Cores ranging from a Single Data Rate 4X core (10GBit/Second) to a Quad Data Rat…
Xilinx provides a flexible Block Memory Generator core to create compact, high-performance memories running at up to 450 MHz The …
The PLBv46 to PCI Full Bridge design provides full bridge functionality between the Xilinx PLB and a 32-bit Revision 2.2 complian…