Vendor: Xilinx, Inc. Category: SRAM

Block Memory Generator

Xilinx provides a flexible Block Memory Generator core to create compact, high-performance memories running at up to 450 MHz The …

Overview

Xilinx provides a flexible Block Memory Generator core to create compact, high-performance memories running at up to 450 MHz

The Block Memory Generator LogiCORE™ IP core automates the creation of resource and power optimized block memories for Xilinx FPGAs. Available through the (add ref to Vivado™) ISE® Design Suite CORE Generator™ System, the core enables users to create block memory functions to suit a variety of requirements. Built-in knowledge about Xilinx device architectures allow it to leverage specialized FPGA architectural features to create the most compact, high performance or low power solution.

A Migration Kit is available to automate the migration to latest version of the core.

Key features

  • Choice of Native Interface, AXI, or AXI4-Lite
  • Example Design helps you get up and running quickly
  • Native interface core
    • Generates Single-Port RAM, Simple Dual-Port RAM, True Dual-Port RAM, Single-Port ROM, or Dual-Port ROM
    • Performance up to 450 MHz
    • Data widths from 1 to 4096 bits
    • Memory depths from 2 to 128k
    • Variable Read-to-Write aspect ratios in Virtex®-7, Kintex®-7, Virtex-6, Virtex-5 and Virtex-4 FPGAs
    • Option to optimize for resource or power
    • Ability to initialize the memories with pre-defined values
    • Supports individual write enable per byte in Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-4, Spartan®-6 and Spartan- 3A / XA DSP with or without parity.
    • Selectable per-port operating mode: WRITE_FIRST, READ_FIRST or NO_CHANGE
    • Support for hard and soft Error Correction (ECC) feature
  • AXI interface core
    • Generates Dual Port RAM
    • Performance up to 300 MHz
    • Data widths ranging from 8 to 64 bits
  • Common features in Native interface and AXI cores
    • Variable port aspect rations for dual-port configurations
    • VHDL and Verilog behavioral models optimized for fast simulation times
    • Structural simulation model option for precise simulation

Specifications

Identity

Part Number
Block Memory Generator
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA

Learn more about SRAM IP core

A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node

The authors propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects. TCAD calibrated to a state-of-the-art double-gate IGO transistor with a tri-layer HfO2/ZrO2/HfO2 (HZH) gate stack is combined with virtual fabrication and 3D parasitic extraction to realize the first process-aware layout of this topology.

Frequently asked questions about SRAM IP cores

What is Block Memory Generator?

Block Memory Generator is a SRAM IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this SRAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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