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The authors present ArchAgent, a hierarchical multi- agent framework in which an LLM-based planner decomposes system design into chip, scale-up, and scale-out subproblems, each handled by specialist agents.
Panmnesia, a fabless semiconductor company, and Meta, a global hyperscaler, have jointly proposed a next-generation artificial intelligence datacenter architecture in which an entire datacenter operates like a single chip. The work appears as an invited Review in Nature Reviews Electrical Engineering (NREE), a Nature Portfolio journal.
This post provides an in-depth look at the fundamentals of high-speed interconnects, AI/HPC trends (HBM/D2D/CPO), and the three critical requirements of Physical AI: Deterministic Latency, Functional Safety (ISO 26262), and Automotive Reliability (AEC-Q100).
The authors present cMPI, the first work to optimize MPI point-to-point communication (both one-sided and two-sided) using CXL memory sharing on a real CXL platform, transforming cross-node communication into memory transactions and data copies within CXL memory, bypassing traditional network protocols.
The recently released Ultra Ethernet (UE) 1.0 specification defines a transformative High-Performance Ethernet standard for future Artificial Intelligence (AI) and High-Performance Computing (HPC) systems. This paper, written by the specification's authors, provides a high-level overview of UE's design, offering crucial motivations and scientific context to understand its innovations.
The Ultra Ethernet Consortium is introducing a link-layer retry mechanism to avoid costly recovery at higher layers.