CAST IP Listing

The Timer-APB core is a 32-bit counter/timer with an APB interface that can be used to schedule periodic tasks, and can act as a …

• Timers & Watchdogs

The WDT-APB core implements 32-bit count down counter with a programmable timeout interval and logic to generate an interrupt and…

• Timers & Watchdogs

The RTC-APB core implements a real-time clock (RTC) and calendar facility together with an alarm function.

• Timers & Watchdogs

The TSN-SW implements a flexible, low-latency, multiport TSN Ethernet switch.

• Ethernet

Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection.

• Ethernet

The TSN-SE implements a configurable controller meant to ease the implementation of switched endpoints for Time Sensitive Net-wor…

• Ethernet

The LLEMAC-1G implements an Ethernet Media Access Controller (MAC) compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.…

• Ethernet

The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time …

• Ethernet

The JPEG-LS-E core implements a efficient, low-power, lossless and near-lossless image compression engine that is compliant to th…

• Image Conversion

The JPEG-LS-D core implements a efficient and low-power, lossless and near-lossless image decompression engine that is compliant …

• Image Conversion

The SPMI-CTRL core implements a featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus.

• MIPI

The xSPI-MC core is a versatile serial/SPI memory controller, which allows a system to easily detect and access the attached memo…

• SPI / QSPI XSPI

The AES-XTS encryption IP core implements hardware encryption/decryption for sector-based storage data.

• AES

The Geon™ Secure Execution Processor is a low-power, 32-bit processor IP core with built-in protection of sensitive code and data.

• Security Coprocessor

Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection.

• Ethernet

This Video Over IP Subsystem employs JPEG compression and RTP/UDP/IP encapsulation to enable the rapid development of motion JPEG…

• Video Processing

The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave processor interface and a 32-bit master int…

• Bus Fabric

The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256.

• SHA2 (SHA-256)

The MD5 encryption IP core is a fully compliant hardware implementation of the Message Digest Algorithm MD5, suitable for a varie…

• Hash / MAC

The KEXP IP core performs AES key expansion, and is an option for the AES, AES-P, AES-CCM and AES-GCM cores.

• AES