AHB Cache Controller

The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave processor interface and a 32-bit master interface to the memory subsystem. The processor and memory interfaces are natively AHB5 and can easily be reduced to AHB-lite. 

The cache controller core supports a four-way associative cache memory and implements a Least Recently Used (LRU) replacement policy. The number of cache lines and the cache line width are configurable at synthesis time. The core only caches read accesses and invalidates the cached data if a write-access to a cached memory location occurs.  

Mapping the cache controller to any technology is straightforward, as the core does not require any special type of SRAM modules, only using standard, single-ported SRAMs. Furthermore, the design is scan-ready as it uses only rising-edge triggered flip-flops and contains no internal tri-states. Integration of the core is trouble-free, as the core uses standard 32-bit AHB interfaces and supports clock gating. 
The CACHE-CTRL core has been robustly verified and is silicon-proven.  

The CACHE-CTRL can be used to add single or multilevel cache memory to cache-less deeply embedded processors, DSPs, or ASIPs. This can decrease the read access time and bandwidth to a relatively slow or energy-consuming memory resource like flash, EEPROM, or DRAM devices. For example, it allows embedded processors like the BA2x, or the RISC-V BA51, or ARM’s Cortex-M to run code directly from an off-chip NOR-flash (XIP) while minimizing the typical performance and/or power penalties of off-chip access.

• Adds single or multilevel cache memory to originally cache-less deeply embedded processors, DSPs, or ASIPs.
  Improves access time and reduces bandwidth to DRAM, Flash or EEPROM memories; enables XIP without typical power or performance penalties.
• Cache Parameters
  • Four-way set-associative cache
  • Least Recently Used (LRU) replacement policy
  • Synthesis-time configurable:
    • number of cache lines
    • number of words per line
  • 32-bit words 
  • Invalidates cache contents if a write access occurs
• Easy Integration & Implementation
  • AHB5 or AHB-lite interfaces
    • 32-bit slave port towards the processor
    • 32-bit master port towards the memory system
  • Uses four single-ported SRAMs: no special type of RAM is required
  • Scan-ready design
  • Supports clock gating