On-the-fly decryption engine FRTDEC allows to decrypt on-the-fly AXI traffic based on the read request address information.
- Symmetric Crypto
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
On-the-fly decryption engine FRTDEC allows to decrypt on-the-fly AXI traffic based on the read request address information.
Asymmetric cryptographic accelerator
The ACrypto Engine is an asymmetric cryptographic accelerator suitable for embedded application.
PCIe Controller is a high performance PCIE controller, it can support PCIE 1.0/2.0/3.0/4.0 protocol, and the support speed is 2.5…
XEC is a high performance 1000M/100M/10M Ethernet Controller IP.
The DDR PHY IP is a combination of hard macro, I/O Pad and synthesizable RTL to provide a physical interface to JEDEC standard DD…
The DDR controller (DDR4/LPDDR4 Controller) supports the following SDRAM types: DDR4 LPDDR4 On the host side, DDR4/LPDDR4 Control…
The USB PHY IP is UTMI interface compatible and a dedicated circuit for full-function USB 2.0 transceivers.
The Nuclei Universal Serial Bus (USB) Controller is compliant with the USB 2.0 Specification to support high-speed,full-speed or …
The Display controller (DISP) provides a parallel digital RGB (red, green, blue) and signals for horizontal, vertical synchroniza…
The Graphic 2D Accelerator (G2D) is a specialized DMA dedicated to image manipulation.
CMOS camera.
The GMC (General Memory Controller) includes two memory controllers: The NOR/PSRAM memory controller The Synchronous DRAM (SDRAM/…
Serial Audio Interface/Inter-IC Sound
The SAI interface (Serial Audio Interface) offers a wide set of audio protocols due to its flexibility and wide range of configur…
The Mailbox IP is the communication channel between the internal system and the host processors.
The Basic Timer consists of a 32-bit auto-reload counter driven by a programmable pre-scaler.
The Adv_Timer (-control Timers) consist of a 32-bit auto-reload counter driven by a programmable prescaler.
The Improved Inter Integrated Circuit (I3C) is part of a group of communication protocols defined by the MIPI Alliance.
I2C (Inter-Integrated Circuit) bus Interface serves as an interface between the microcontroller and the serial I2C bus.
CRC (Cyclic Redundancy Check) Calculation Unit
CRC (Cyclic Redundancy Check) calculation unit using a polynomial generator from 8-bit/16-bit/32-bit data words CRC code.
The RTC (Real Time Clock) provides an automatic wake-up to manage all low-power modes.