DDR4/LPDDR4 PHY Interface

The DDR PHY IP is a combination of hard macro, I/O Pad and synthesizable RTL to provide a physical interface to JEDEC standard DDR3/DDR4 SDRAM memories.The synthesizable RTL (ddr_phy_top) provides control functions such as initialization, SDRAM interface training, impedance calibration and programmable configuration controls. It also provides a DFI interface from external DDR controller to hard macros. The register access interface is APB.

• Support JEDEC standard DDR3, DDR4, LPDDR3, LPDDR4 SDRAMs
• Support X4/X8/X16/X32 devices
• Support 1:2 clock mode for controller clock : memory clock
• Many SDRAM packaging options supported:
  • SDRAM components soldered directed to PCB
  • LPDDR4 PoP
  • UDIMMs/RDIMMs
• 8 to 72-bit data path widths in 8-bit increments
• Partially populated interfaces where allowed by protocol
• Supports up to 4 ranks
• Compatible with DFI 4.0
  • Low power control interface is compatible with DFI 3.0
• PHY independent training
  • LPDDR3/LPDDR4 command bus training. For LPDDR4, 2D CS/CA training is supported. That means both CS/CA delay and SDRAM VREFCA can be trained
  • Write leveling to compensate for CK-DQS flight time skew
  • Read gate training
  • Read data eye training, includes: Read DQ bit de-skew training, Read DQS to read DQ eye centering training, PHY IO VREF training per DBYTE
  • Write DQ training. For DDR4 and LPDDR4, 2D write DQ training is supported. That means both write DQ delay and SDRAM VREFDQ can be trained
• VT compensated delay lines for training
  • Automatic periodic updating through PHY update Interface
  • Manually updated by Controller update interface
• Programmable input on-die termination (ODT)
• Programmable output impedance
• PVT-compensated ODT and output impedance
• IO calibration and ODT calibration
• Periodic retraining for SDRAM write (tDQS2DQ) and read (tDQSCK) drift through PHY master interface
• Support up to four distinct trained frequencies to permit fast frequency changes between the four frequencies
  • Each trained frequency has unique frequency and I/O drive and ODT impedance settings
  • Frequency changes are initiated by the DFI interface without software involvement
• Support below low power states:
  • Light sleep mode: Most clocks and delay lines gated
  • Deep sleep mode: In addition to the description of light sleep mode, memory clocks are also gated
  • Retention: Core power removed, most I/Os powered down, SDRAMs held in self-refresh
• Flexible pre and post amble
  • Support for 1 or 2 tCK write preamble
  • Support for 0.5 or 1.5 tCK write postamble
  • Support for 1 or 2 tCK read preamble
  • Support for 0.5 or 1.5 tCK read postamble
• Support DDR4 gear down mode
• Support for a SW controllable DQ bit and AC bit swap
• APB and JTAG interfaces for register access
• Test support:
  • At-speed PAD loopback and internal loopback testing on command, address and data
  • Delay line BIST
  • MUX-scan ATPG
  • MBIST for testing SDRAM
  • Boundary scan interface