How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Nuclei System Technology
Category:
DDR
General Memory Controller
The GMC (General Memory Controller) includes two memory controllers: The NOR/PSRAM memory controller The Synchronous DRAM (SDRAM/…
Overview
The GMC (General Memory Controller) includes two memory controllers:
- The NOR/PSRAM memory controller
- The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
Key features
- Interface with static-memory mapped devices including:
- Static random access memory (SRAM)
- NOR Flash memory/OneNAND Flash memory
- PSRAM (4 memory banks)
- Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
- Burst mode support for faster access to synchronous devices such as NOR Flash memory, PSRAM and SDRAM)
- Programmable continuous clock output for asynchronous and synchronous accesses
- 8-,16- or 32-bit wide data bus
- Independent Chip Select control for each memory bank
Specifications
Identity
Part Number
GMC
Vendor
Nuclei System Technology
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
China
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
DDR IP Hardening - Overview & Advance Tips
DDR is most critical IP to SoC’s successful operation, because processors in SoC typically spends the majority of its cycles on reading and writing to DDR memory.
Which DDR SDRAM Memory to Use and When
This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
DDR5/4/3/2: How Memory Density and Speed Increased with each Generation of DDR
Frequently asked questions about DDR Interface IP
What is General Memory Controller?
General Memory Controller is a DDR IP core from Nuclei System Technology listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.