DDR4/LPDDR4 Controller

The DDR controller (DDR4/LPDDR4 Controller) supports the following SDRAM types:

• DDR4
• LPDDR4

On the host side, DDR4/LPDDR4 Controller supports up to 16 AMBA4 AXI. The configuration registers are programmed through the APB interface.
On the DFI side, DDR4/LPDDR4 Controller supports for intergration with DFI4.0-compliant PHY.

• DFI4.0 interface including:
  • write data and read data interface
  • controller initiated and phy initiated update interface
  • phy initiated master interface
  • low power interface
  • only support PHY-Independent training mode
• 1:2 frequency ratio
• Software triggered and hardware triggered ZQ short calibration
• ZQ long calibration after self-refresh exit for DDR4
• ZQ Cal/Latch after self-refresh exit for LPDDR4
• Configurable CAMs used to do out of order scheduling to optimize bandwidth usage and latency
• Programmable SDRAM timing parameters
• Programmable SDRAM data-bus width, support full-bus width or half-bus width(only for DDR4)
• Support 1, 2, or 4 memory ranks
• Support BL8 read and write operation with burst chop for DDR4
• Support BL16 read and write operation for LPDDR4
• Guaranteed coherency for address collision like write-after-read (WAR) and read-after-write (RAW)
• Supports automatic SDRAM power-down entry and exit caused by lack of transaction arrival for a programmable time
• Supports automatic SDRAM self refresh entry and exit caused by lack of transaction arrival for a programmable time
• Software triggered self-refresh entry and exit
• Support for SDRAM mode register updates under software control
• Flexible address mapping logic
• Intelligent refresh control when the controller is idle for a programmable period of time
• Smart power-saving design to prevent unnecessary toggling of command, address and data
• Support fine granularity refresh when working in DDR4 mode
• Support data bus inversion (DBI)
• Support Maximum power saving mode(MPSM) when working in DDR4 mode
• Support Multi-purpose Register(MPR) reads and writes when working in DDR4 mode
• Support Per DRAM addressability(PDA) when working in DDR4 mode
• Support Command/address latency when working in DDR4 mode
• Support Sideband ECC(SECDED) for DDR4
• Support Inline ECC(SECDED) for both DDR4 and LPDDR4
• Programmable AXI port number and AXI data width, support up to 16 axi ports
• Support asynchronous axi clock
• Support for AXI incremental and wrap burst type
• Support for AXI read data out of order and interleaving