The USB 2.0 Host Controller IP Core is a 32-bit Avalon/AXI/AHB interface compliant core and supports ULPI interface.
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Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The USB 2.0 Host Controller IP Core is a 32-bit Avalon/AXI/AHB interface compliant core and supports ULPI interface.
USB 2.0 Device with FIFO Interface (USB20HF)
USB 2.0 device, FIFO interface (USB20HF) IP Core provides FIFO interface for endpoints and ULPI interface for Host communication.
The SD/eMMC Host Controller IP Core implements the SD Physical Layer v3.0 and eMMC Physical Layer v4.51 compatible Host Controlle…
Floating-point to Fixed-point Converter
Converts 32-bit floating-point numbers to fixed-point representation.
Fixed-point to 32-bit floating-point converter
FIXED_TO_IEEE is a high-speed fully pipelined conversion unit that accepts a signed fixed-point number as input and generates a 3…
32-bit Floating-point Divider IP Core
High-speed fully pipelined 32-bit floating-point divider based on the IEEE 754 standard.
High-speed fully pipelined 32-bit floating-point adder/subtractor based on the IEEE 754 standard.
High-speed fully pipelined 32-bit floating-point multiplier based on the IEEE 754 standard.
N-channel Multiplexed FIR Filter
FIR_NTAP_MUX is an N-channel multiplexed FIR filter designed for high sample rate applications where hardware resources are limit…
IIR Filter Second-Order-Section
2nd order IIR filter sometimes referred to as a 'bi-quad'.
Half-band Nyquist Decimation Filter
FIR_DEC_N is a polyphase decimation filter that permits the down sampling of an input signal by any power of 2.
Generic high-speed FIR Filter with symmetry
FIR filter designed for high sample rate applications with symmetrical coefficients and an even or odd number of taps.
Generic ultra-speed FIR Filter
FIR filter designed for very high sample rate applications up to 600 MHz.
64 State 4x8PSK (4D 8PSK) CCSDS ECSS Viterbi Decoder
The VA06C is a fully parallel 64 state error control decoder using the maximum likelihood Viterbi algorithm for the 4x8PSK (4D 8P…
Our FPGA core is optimized and 80% SMALLER THAN THE COMPETITION!
10Gbps Low Latency Ethernet Solution
The 10Gbps 32-bit Ethernet IP solution offers a fully integrated IEEE802.3-2008 (802.3ae) compliant package for NIC (Network Inte…
RSA public key cryptography with APB interface
The standard RSA module is available as an APB peripheral, where it seamlessly integrates with EnSilica's cryptography library.
SATA III HOST Controller on Virtex 6
The LDS SATA 3 HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 speed grade 2 …
High-Speed Digital PLL (0.5-7.5 GHz) in TSMC 40G CMOS
Granite SemicCom's Digital PLL is intended for applications such the Clock-Multiplying-Unit in a SERDES or a Clock-Driver with fr…
The ntI2C_M is an I2C-bus multi-master interface controller and provides a cost-effective solution for a wide range of applicatio…