Vendor: A2e Technologies Category: Video Processing

H.264 CODEC FPGA Core

Our FPGA core is optimized and 80% SMALLER THAN THE COMPETITION!

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H.264 / AVC View all specifications

Overview

Our FPGA core is highly optimized and 80% SMALLER THAN THE COMPETITION! It is capable of being synthesized in Xilinx FPGAs and supports H.264 variable and fixed bit-rate encoding of video streams. Encodes video data at 1.5 clocks/pixel. Typical clock rate in an Xilinx SPARTAN 6 is 95Mhz. Typical clock rate in a Xilinx Zynq 7020 is 95MHz. Multiple cores can be used for processing larger size or higher frame rate images. Uses FPGA specific DDR 3 controller and microprocessor soft core. In addition, the standard core can be customized, retaining ITAR compliance, to meet unique functional needs.

Key features

  • Designed for high-speed, high-pixel count CMOS sensors interfacing to medium to high-bandwidth connections
  • 1.5 clocks/pixel processing rate
  • Built in H.264 Decoder that can decode A2e specific H.264 encoded streams
  • Fully compatible with the ITU-T H.264 specification
  • Supports resolutions up to 4096 x 4096 (can be expanded with additional cores)
  • Supports simultaneous encoding of multiple streams of arbitrary sizes and compression ratios
  • Generates I and P frames
  • Variable Bit Rate (VBR) and Constant Bit Rate (CBR)
  • Search range: 80 X 48 pixels, Full, 1/2, 1/4 pixel resolution
  • Entropy Encoding: CAVLC-
  • Support for intra 4 x 4 DC prediction
  • Support for Single or Multiple slices via firmware control
  • Supports YUV 4:2:0 video input
  • Fully synchronous design
  • Available as FPGA specific netlist
  • Custom versions available

What’s Included?

  • Binary or source code licenses available

Specifications

Identity

Part Number
2.22000
Vendor
A2e Technologies
Type
Silicon IP

Compute

Codec Standard
H.264 / AVC

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact A2e Technologies

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is H.264 CODEC FPGA Core?

H.264 CODEC FPGA Core is a Video Processing IP core from A2e Technologies listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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