TSMC CLN28HPC 28nm Deskew PLL - 700MHz-3500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 28nm
- HPC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
TSMC CLN28HPC 28nm Deskew PLL - 700MHz-3500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CLN28HPC 28nm DDR DLL - 150MHz-750MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN28HPC 28nm DDR DLL - 200MHz-1000MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN28HPC 28nm DDR DLL - 316MHz-1580MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN28HPC 28nm Clock Generator PLL - 175MHz-875MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPC 28nm Clock Generator PLL - 350MHz-1750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPC 28nm Clock Generator PLL - 700MHz-3500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
Common Public Radio Interface (CPRI) v.6.1 IPC
CPRI (Common Public Radio Interface) is an interfacing standard for high-speed communication of digital radio samples and control…
The nSAD_TS180_1V8_AD14b2M is a 14b 2MS/s, 13 ENOB, low-power SAR fully-differential AD converter designed on the TSMC 180 proces…
Reconfigurable Parallel CRC Generator
Parallel CRC IP is reconfigurable high-speed CRC generator, flexible in terms of input data width and generating polynomial.
The MVD Multi-RTP transmitter allows the transmission of several RTP streams on an Ethernet Network.
DPA Resistant Software Library
Addressing the growing demand for readily available solutions that implement Differential Power Analysis (DPA) countermeasures, w…
Emulation of RF and channel impairments in Verilog
The BAY9 Virtual RF (VRF) is an IP core written in Verilog, that allows to emulate most system aspects of a typical RF transmissi…
Silicon-proven, High Density and Low Power Static Random Access Memories
Spectral MemoryIP™ is set of silicon-proven, High Density and Low Power Static Random Access Memories.
Multi Function Viterbi Decoder
The VA08VA is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
100G Reed-Solomon Codec for Ethernet IEEE 802.3 Clause 91 (803.3bj)
The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 80…
ISO/EIC 7816 and EMV4.3 UART, with protocol controller and timers
The ISO7816 UART contains all of the digital logic necessary to communicate with an ISO/IEC 7816 or EMV 4.3 integrated circuit ca…
8-Channel PCM-to-PWM Modulator in Fujitsu 55nm
The AR35F01A is a digitally coded conversion IP that translates 8-ch (4 stereo channels) of 16-24bit pulse-code modulated (PCM) i…
3.3V to 1.2V voltage regulator - UMC 55nm
The cell is a low power series 3.3V to 1.2V voltage regulator.
UMC L28HLP 28nm Multi Phase DLL - 110MHz-550MHz
The Multi Phase DLL is designed for high-speed interface applications.