Vendor: Aragio Solutions Category: GPIO

I2C I/O Pad Set

The I2C libraries provide the bidirectional I/O for two-line serial communication per Rev.

Contact Provider Request Datasheet
TSMC 16nm Pre-Silicon View all specifications

Overview

The I2C libraries provide the bidirectional I/O for two-line serial communication per Rev. 4 of the I2Cbus industry specification. The design is compatible with Standard-mode, Fast-mode, and Highspeed mode I 2C operating modes.

Key features

  • I2C Bi-directional Driver Features
    • Supported I2C operating modes:
      • Standard-mode (Sm) – 100 Kbps data rate
      • Fast mode (Fm) – 400 Kbps data rate
      • Fast mode (Fm+) – 1.0 Mbps data rate
      • High-speed mode (Hs) - 3.4 Mbps data rate
    • Open drain operation only
    • Built-in output slew rate control to meet I2C Tof minimum of (20 x VDDP/5.5V) ns
    • Output enable and mode select
    • Receiver enable
    • ESD protection is accomplished with an SCR (no diode to the positive power supply)
    • Standard LVCMOS compatible input with optional Schmitt trigger (hysteresis)
    • Power-on sequencing independent design with Power-On Control
    • DVDD = 1.62V to 1.98V
    • Pad VDDP = 1.62V to 1.98V – independent of DVDD
    • The circuit consumes no DC supply current in the static state
    • Fault-tolerant to 1.98V at PAD (no current flow when DVDD = 0V)
  • An open-drain design, this cell requires an external pull-up resistor to a high voltage power supply. Designed for a 1.8V I2C bus application, VDDP can track DVDD but it is not necessary. The sizing of the external resistor or appropriate pull-up network is application dependent.

What’s Included?

  • Physical abstract in LEF format (.lef)
  • Timing models in Synopsys Liberty formats (.lib and .db)
  • Calibre compatible LVS netlist in CDL format (.cdl)
  • GDSII stream (.gds)
  • Behavioral Verilog (.v)
  • Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • Databook (.pdf)
  • Library User Guide - ESD Guidelines (.pdf)

Silicon Options

Foundry Node Process Maturity
TSMC 16nm 16nm 160 nm Pre-Silicon

Specifications

Identity

Part Number
RGO_TSMC05_15V18_N5_45F_I2C
Vendor
Aragio Solutions
Type
Silicon IP

Provider

Contact Aragio Solutions

Learn more about GPIO IP core

GPIO Solutions for CERN’s Radiation-Hardened Applications

For over a decade, Sofics has collaborated with CERN, the European Organization for Nuclear Research. Sofics has delivered advanced GPIO cells tailored for radiation-hardened applications, supporting CERN’s groundbreaking particle physics experiments.

A Generic Solution to GPIO verification

This paper provides a complete solution to the GPIO Verification for any SoC. GPIO interface is available in every ASIC. To avoid duplicate efforts and (save) time to verify the GPIO interface, we have produced this Generic GPIO verification suite. It is a UVM-based verification environment, with all the necessary subcomponents that are required to verify any GPIO design.

How AI and Edge Computing Are Accelerating RISC-V Adoption

One of the critical problems in today’s computing is that transporting data can be more costly in energy and time than computing. With the growing complexity of AI models, SoC designers have shifted their focus toward optimizing memory hierarchies, increasing bandwidth in interconnects, and architecting based on workloads for improved efficiency.

Ensuring reliability in Advanced IC design

To complete our task as engineers we rely on the tools we use. We collaborated with Siemens EDA solutions back in 2025 on a webinar about how we use their tools to develop our designs and layouts.

Integrating Post-Quantum Cryptography (PQC) on Arty-Z7

Post-quantum cryptography (PQC) is moving from theory to engineering reality. With NIST-standardized algorithms ML-KEM (FIPS 203) and ML-DSA (FIPS 204) now finalized, FPGA developers face a practical challenge: How to integrate these algorithms efficiently on resource-constrained hardware?

Frequently asked questions about GPIO Pad Library IP cores

What is I2C I/O Pad Set?

I2C I/O Pad Set is a GPIO IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for tsmc Pre-Silicon.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP