224G Ethernet PHY, Intel 18A x4, North/South (vertical) poly orientation
The 224G Ethernet PHY IP, an integral part of the high-speed SerDes IP portfolio, meets the growing high bandwidth and low latenc…
Rambus is offering the industry’s first HBM4 Controller IP core designed to support customers with deploying a new generation of …
6GHz-12.5GHz PLL in GF 22nm FDX
Ultra-low jitter, low-power ring-oscillator-based PLL- 6GHz-12.5GHz in GF 22nm FDX
UCIe-S PHY for Standard Package (x32) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
UCIe-S PHY for Standard Package (x16) for Automotive in TSMC (N5A)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
UCIe-A PHY for Advanced Package (x64) in Samsung (SF2)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
UCIe-A PHY for Advanced Package (x64) in TSMC (N5)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
UCIe-A PHY for Advanced Package (x64) in Samsung (SF4X)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
Most advanced PHY and controller IP for HPC, AI/ML, data communications, networking, and storage systems
The Synopsys Ethernet 400G and 200G Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3bs standard and provides a …
Die-to-Die, High Bandwidth Interconnect PHY in TSMC (N7, N5)
The Synopsys High-Bandwidth Interconnect PHY IP enables high bandwidth, low-power and low-latency die-to-die connectivity in a pa…
UCIe-A PHY for Advanced Package (x64) in TSMC (N7, N6, N5, N3)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
112G Ethernet PHY in TSMC (N7, N5, N3P)
The Synopsys 112G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth…
224G Ethernet PHY in TSMC (N3E)
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth…
The Bitec HDMI 2.1b IP Core enables HDMI interconnectivity in FPGA or ASIC devices.
The Compute Express Link® (CXL®) 3.1 Controller is a parameterizable design for ASIC and FPGA implementations.
Low-power, long-reach, multi-protocol PHY for PCIe 4.0
14GHz Integer-N High-Speed PLL
1-VIA’s broad portfolio of general-purpose and optimized LC-PLLs offer a wide range of clocking solutions.