World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
Synopsys delivers standards-compliant 112G PHY IP for linear optics, helping reduce AI interconnect power, latency, and heat.
Vendor:
Synopsys, Inc.
Category:
UCIe
UCIe-S PHY for Standard Package (x16) for Automotive in TSMC (N5A)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
Overview
Synopsys UCIe PHY IP enables high-bandwidth, low-power and
low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The PHY’s flexible architecture supports standard and advanced package technologies and delivers up to 4Tbps bandwidth
in a multi-module configuration. Supporting widely used protocols such as PCI Express and CXL and enabling latency-optimized NoC-to-NoC links with streaming protocols, the IP offers maximum performance, minimum latency and implementation flexibility. Synopsys UCIe PHY IP delivers high energy- efficiency with an optimized architecture that uses clock forwarding and
low-voltage signaling. The IP implements a comprehensive set of testability features to ensure known good dies and offers test and repair capabilities to improve package assembly yield. Robust die-to-die link operation is ensured with embedded training and calibration algorithms.
Synopsys UCIe PHY IP interoperates with Synopsys UCIe Controller IP to deliver a complete, low-latency solution for die-to-die links in any package.
low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The PHY’s flexible architecture supports standard and advanced package technologies and delivers up to 4Tbps bandwidth
in a multi-module configuration. Supporting widely used protocols such as PCI Express and CXL and enabling latency-optimized NoC-to-NoC links with streaming protocols, the IP offers maximum performance, minimum latency and implementation flexibility. Synopsys UCIe PHY IP delivers high energy- efficiency with an optimized architecture that uses clock forwarding and
low-voltage signaling. The IP implements a comprehensive set of testability features to ensure known good dies and offers test and repair capabilities to improve package assembly yield. Robust die-to-die link operation is ensured with embedded training and calibration algorithms.
Synopsys UCIe PHY IP interoperates with Synopsys UCIe Controller IP to deliver a complete, low-latency solution for die-to-die links in any package.
Key features
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange
- Built-in self-test (BIST), internal loopback, and external PHY-to-PHY link test
- Flexible configuration: 64 RX and TX pins per module (advanced package) or 16 RX and TX pins per module (standard package)
- Built-in test and repair functionality with redundant pins to maximize yield
- NS (north, south) orientation, EW (east, west) possible
Benefits
- Delivers up to 4Tbps with up to 5.2Tbps/ mm of die edge
- High-bandwidth, low-power, low-latency multi-module PHY for applications requiring reliable connections between dies within a package; Partitioning a large SoC into multiple smaller SoCs for flexibility in configuration or for improving yield; Packaging multiple SoCs to create complex subsystems; Connecting a SoC to smaller dies containing multiple lanes of SerDes or other functions to implement the SoC in a different process node or foundry than that of the smaller dies
- Supports advanced packaging technologies such as silicon interposer, silicon bridge or RDL fanout
- Supports standard packaging technologies such as organic substrate or laminate
Applications
- Multi-Die SoC for: High-performance computing and servers; Artificial intelligence / machine learning; Networking and infrastructure; Consumer and mobile
What’s Included?
- Verilog models and test bench
- Protocol-specific test bench
- Liberty™ timing views (.lib), LEF abstracts (.lef), CDL netlist (.cdl)
- GDSII
- IP-XACT XML files with register details
- ATPG models
- IBIS-AMI models
- Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 5nm | N5A | — |
Specifications
Identity
Part Number
dwc_ap_ucie_1ts4_tsmc
Vendor
Synopsys, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about UCIe IP cores
What is UCIe-S PHY for Standard Package (x16) for Automotive in TSMC (N5A)?
UCIe-S PHY for Standard Package (x16) for Automotive in TSMC (N5A) is a UCIe IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this UCIe?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UCIe IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.